An electrically erasable programmable semiconductor storage element capable of retaining data even after power is shut off is called the nonvolatile semiconductor memory (NVSM). NVSM cells of this type are becoming more important for use as storage media in advanced electronics equipment, including handheld or “mobile” information processing tools. Today, these memories are in progress of development for achieving ultra-low voltage drivability and extra-large storage capacity. One of currently major NVSMs is a “Flash” memory of the type storing data by accumulation of electrical charge on a floating electrode made of polycrystalline silicon or “poly-silicon,” which is disclosed, for example, in R. Bez et al., “Introduction to flash memory,” Proceedings of the IEEE, Vol. 91, No. 4, pp. 489-502 (2003).
Unfortunately, flash memories with the floating electrode made of polysilicon suffers from a limit in miniaturization of on-chip circuit elements. This can be said because the polysilicon floating electrode is difficult in scaling in its lengthwise direction, posing a problem as to unwanted interference between adjacent memory cells occurring due to capacitive coupling therebetween. Another reason is that electrical charge carriers residing on the floating electrode are all disappeared upon occurrence of pin holes in a tunnel oxide film that serves to suppress leakage of charge between the floating electrode and its underlying substrate. This causes a problem as to the difficulty in making the tunnel oxide film thinner by thin-film fabrication processes. Accordingly, in recent years, diligent studies and researches are made to develop new NVSM devices in place of the existing flash memories.
One of such new NVSM devices is a silicon-oxide-nitride-oxide-silicon (SONOS) memory, which stores data by storing charge in a silicon nitride film. Teachings as to this SONOS memory are found in M. H. White et al., “On the go with SONOS,” IEEE Circuits and Devices, Vol. 1, No. 4, pp. 22-31 (2000). See FIG. 33, which shows a typical sectional structure of SONOS memory.
This SONOS memory has a silicon substrate 100 of p type conductivity, with a channel region 105 is formed therein. On a surface of this channel region 105, a tunnel dielectric film 120 is formed, which is made of silicon oxide. On this tunnel insulator film 120 a charge storage dielectric film 122 made of silicon nitride is formed. On this charge storage dielectric film 122 a control dielectric film 124 is formed, which is made of silicon oxide. Further, on this film 124 a control electrode 130 is formed, which is made of heavily-doped n (n+) type polysilicon. At both ends of the channel region, a source region 141 and drain region 143 are formed, which are made of n+-type silicon.
This device structure is thought to be equivalent to an n-channel field effect transistor (FET) having three terminals—i.e., the source/drain regions in Si substrate and control electrode—with a gate insulator film beneath the control electrode being replaced by a multilayer structure of the control dielectric film 124, charge storage dielectric film 122 and tunnel insulator film 120. The silicon nitride film making up the charge storage dielectric film 122 has a trap level. The charge storage dielectric film 122 is electrically insulated by the tunnel insulator film 120 from the Si substrate 100. The charge storage dielectric film 122 is electrically insulated by the control dielectric film 124 from the control electrode 130 also. Accordingly, the charge storage dielectric film 122 which has its trap level and which is insulated from its surrounding—namely, electrically floating—is capable of storing thereon electrical charge carriers.
To program or “write” data into this memory cell, a voltage of the positive polarity is applied between the Si substrate 100 and the control electrode 130, thereby causing electrons to be injected by quantum tunneling phenomena from the channel region into the charge storage dielectric film 122 made of silicon nitride. To read data out of this memory cell, a read voltage is applied between the source and drain regions 141 and 143 and also between the source region 141 and control electrode 130. The amount of a current flowing from the source region 141 to drain region 143 is different between a state that the SiN charge storage dielectric film 122 retains the injected electrons and thus is charged negatively and a state that no electrons are injected thereinto. Thus, by detecting this current value difference, in other words, a difference in transistor's threshold voltage, it is determinable whether the data is a logic “0” or “1.”
To lower read error rates, it is desirable to enlarge the current value difference between the electron-injected state and no electron-injected state of the SiN charge storage dielectric film 122. One approach to doing so is to increase a difference of transistor threshold voltages, which will be referred to hereinafter as threshold voltage shifts. In order to enlarge the threshold voltage shifts in SONOS memories, it is considered to increase the volume of the charge storage dielectric film for storage of electrical charge—for example, make this film thicker.
In addition, in order to lengthen the data retention time that is one of the most important performance requirement for NVSM devices, a need is felt to sufficiently thicken the tunnel insulator film 120. This is because of the fact that if this tunnel insulator film is thin, its current leakage increases, resulting in a decrease in length of the data retention time.
However, simply thickening the charge storage dielectric film and the tunnel insulator film accompanies the risk of an unwanted increase in voltage needed when performing writing based on tunneling. This is a bar to achievement of ultralow voltage drivability. In addition, it becomes difficult to suppress short-channel effects, which in turn makes it difficult to miniaturize memory cell size dimensions by shortening the distance between source/drain regions, called the channel length. In other words, it becomes difficult to attain large capacity storage performance required.
One approach to avoiding the downscaling difficulty is to employ a three-dimensional (3D) device structure of the fin type, called the fin field effect transistor (FinFET) structure, to thereby suppress short-channel effects while at the same time letting the charge storage dielectric film and tunnel insulator film be kept thin. This method is disclosed in U.S. Pat. No. 6,963,104 B2 to Wu et al.
A micro-crystalline silicon memory device is also under study along with researches for SONOS memories, which device stores data through accumulation of charge at a silicon microcrystal or “nanocrystal” layer. A sectional view of a cell structure of this silicon nanocrystal memory is shown in FIG. 34.
This memory cell is similar in structure to the SONOS memory shown in FIG. 33, with the SiN film being replaced by an electrically conductive silicon nanocrystal grain layer 123. This cell stores data by injection of electrons into the silicon nanocrystal grain layer 123.
Regarding this memory cell, a fine line type 3D structure has been proposed, which has a channel region of not a planar structure but a fin type structure with its height reduced in order to enlarge the threshold voltage shift and lengthen the data retention time. For detail, see M. Saitoh et al., “Effects of ultra-narrow channel on characteristics of MOSFET memory with silicon nanocrystal floating gates,” International Electron Devices Meeting (IEDM), pp. 181-184 (2002). An upper plan view of this fine-line silicon nanocrystal memory cell is shown in FIG. 35. Its sectional view taken along line A-A of FIG. 35 is depicted in FIG. 36 whereas a sectional view along line B-B is shown in FIG. 37.
As shown in FIGS. 36-37, this memory cell is fabricated by use of a silicon-on-insulator (SOI) substrate 100 having a buried oxide film 102 and an upper silicon layer thereon. In the Si layer of SOI substrate 100, a channel region 105 is formed. On both sides of this channel region 105, a source region 141 and drain region 143 are formed, which are made of n+-type silicon. Channel region 105 is of the fine-line 3D structure having its width (W) in the channel length direction (i.e., direction extending from the source to drain region) and height (H), each of which is set to 10 nanometers (nm) or below. The cell also includes a tunnel insulator film 120 made of silicon oxide, which is formed to surround the surface of channel region 105. This tunnel insulator film 120 has its surface on which the conductive silicon nanocrystal grain layer 123 is formed. This layer 123 has a surface on which a control dielectric film 124 made of silicon oxide is formed. On this film 124, a control electrode 130 is formed, which is made of n+-type polysilicon.
An advantage of this fine-line 3D silicon nanocrystal memory over standard silicon nanocrystal memories having a planar channel region has been reported to lie in its ability to achieve both the downscaling of cell size and the lowering of the write voltage by lessening the thickness of the tunnel insulator film.
Unfortunately, even the SONOS memory having fin-type channel region and the fine-line silicon nanocrystal memory are faced with difficulties in achieving further advances in low-voltage drivability and large capacity storability (miniaturization). More specifically, it is still difficult for these known memories to establish increased threshold voltage shifts, long data retention time and reduced variations in characteristics between memory cells, which are strictly required to attain further miniaturization.